 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ! " #$% &" ' ( ) *+ , , --. % /" 01 ( &-2 & " % " 3 " ! " 4 + , , -- " ! / &5# 6 6 &57' " // / ! &57' " " &57' " % " " 6 89 :9: enable pwm mosfet driver with dead time control v in v sw pgnd prdy v dd v sws2 v sws1 mosfet driver with dead time control v in v sw pgnd prdy v dd v sws2 v sws1 pin # pin name pin function 1 v dd supply voltage for the internal circuitry. 2 enable when set to logic level high, internal circuitry of the device is enabled. when set to logic level low, the prdy pin is forced low, the control and sychronous switches are turned off, and the supply current reduces to 10a. 3 pwm ttl-level input signal to mosfet drivers. 4 prdy power ready - this pin indicates the status of enable or v dd . this output will be driven low when enable is logic low or when v dd is less than 4.4v (typ.). when enable is logic high and v dd is greater than 4.4v (typ.), this output is driven high. this output has a 10ma source and 1ma sink capability. 5, 7 pgnd power ground - connection to the ground of bulk and filter ca p acitors. 6 v sw switching node - connection to the output inductor. 8 v in input voltage pin. external bypass ceramic capacitors must be added directly next to the block. 9 v sws1 floating pin. for internal use. externally, short to v sws2 pin only . 10 v sws2 floating pin. for internal use. externally, short to v sws1 pin only . package description interface connection parts per bag parts per reel t & r orientation IP2003Apbf lga 10 --- IP2003Atrpbf lga --- 1000 fig 12 downloaded from: http:/// - !"#" " $ # %! & " ' $ $ ()) ((" * '+ ,! ! " absolute maximum ratings: parameter symbol min typ max units conditions v in to pgnd v in --1 6v v dd to pgnd v dd --6 . 0v pwm to pgnd pwm -0.3 - v dd +0.3 v not to exceed 6.0v enable to pgnd enable -0.3 - v dd +0.3 v not to exceed 6.0v output rms current i out --4 0a measured at v sw recommended operating conditions: parameter s y mbol min typ max units conditions supply voltage v dd 4.6 5.0 5.5 v input voltage v in 3.0 - 13.2 v output voltage v out 0.8 - 3.3 v output current i out --4 0a operating frequency fsw 300 - 1000 khz operating duty cycle d - - 85 % block temperature t blk -40 - 125 c electrical specifications @ v dd = 5v (unless otherwise specified): parameter symbol min typ max units conditions block power loss p loss - 9.4 11.7 w v in =12v, v out =1.3v turn on delay t d(on) -6 3- i out =40a, f sw =1mhz turn off delay t d(off) -2 6- l = 0.3h v in quiescent current i q-vin --1 . 0m a enable = 0v, v in =12v v dd quiescent current i q-vdd -1 0- a enable = 0v, v dd =5v under-voltage lockout uvlo start threshold v start 4.2 4.4 4.5 v hysteresis v hvs-uvlo -1 5 0- m v enable enable input voltage high v ih 2.1 - - v input voltage low v il --0 . 8 power ready prdy logic level high v oh 4.5 4.6 - v v dd =4.6v, i load =10ma logic level low v ol -0 . 10 . 2 v dd -! 0 5 10 15 20 25 30 35 40 output current (a) 0 2 4 6 8 10 12 14 16 p o w e r l o s s ( w ) maximum typical v in = 12v v out = 1.3v f sw = 1mhz t blk = 125c l = 0.30h 0 10 20 30 40 50 60 70 80 90 100 110 120 130 pcb temperature (c) 0 4 8 12 16 20 24 28 32 36 40 o u t p u t c u r r e n t ( a ) safe operating area v in = 12v v out = 1.3v f sw = 1mhz l = 0.30h tx downloaded from: http:/// 7 *< . / ! " = % & 0 / ! " = % & 0 / < = % & 0 / < = % & 0 / 7 3 4 5 6 7 8 9 10 11 12 13 input voltage (v) -1 0 1 2 3 4 5 6 7 s o a t e m p a d j u s t m e n t ( c ) 0.96 1.00 1.04 1.08 1.12 1.16 1.20 1.24 1.28 p o w e r l o s s ( n o r m a l i z e d ) v out = 1.3v i out = 40a f sw = 1mhz l = 0.3h t blk = 125c 0.1 0.3 0.5 0.7 0.9 output inductance (h) 0.98 1.00 1.02 1.04 1.06 p o w e r l o s s ( n o r m a l i z e d ) -0.5 0.0 0.5 1.0 1.5 s o a t e m p a d j u s t m e n t ( c ) v in = 12v v out = 1.3v i out = 40a f sw = 1mhz t blk = 125c 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 output voltage (v) 0.96 1.00 1.04 1.08 1.12 1.16 p o w e r l o s s ( n o r m a l i z e d ) -1.0 0.0 1.0 2.0 3.0 4.0 s o a t e m p a d j u s t m e n t ( c ) v in = 12v i out = 40a f sw = 1mhz l = 0.30h t blk = 125c 300 400 500 600 700 800 900 1000 switching frequency (khz) 40 50 60 70 80 90 100 average i dd (ma) does not include prdy current t blk = 25c 200 300 400 500 600 700 800 900 1000 switching frequency (khz) 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 p o w e r l o s s ( n o r m a l i z e d ) -7 -6 -5 -4 -3 -2 -1 0 1 s o a t e m p a d j u s t m e n t ( c ) v in = 12v v out = 1.3v i out = 40a l = 0.30h t blk = 125c downloaded from: http:/// > $./0 #$ " # # ') $) " ( '1 $ )) ' ) ( " "#2 ) 1 #) ( #$ ") 3 " # $2 ) 1 ) $)# 2) '$$ ' $ $ $# " " 2 $ # ( $" ! ') ( # $*4 # ! ' ")) ( $ "# $./0 " ! '$ 5 )) ( $ " ( $ ") ) ' $ $./0" $67 $# '$ "$ $$ 5 )) $67 $./0" to calculate power loss for a given set of operating conditions, the following procedure should be followed: determine the maximum current for each IP2003Apbf and obtain the maximum power loss from fig 1. use the curves in figs. 3, 4, 5 and 6 to obtain normalized power loss values that match the operating conditions in the application. the maximum power loss under the operating conditions is then the product of the power loss from fig. 1 and the normal- ized values. to calculate the soa for a given set of operating conditions, the following procedure should be followed: determine the maximum pcb temperature and case temperature at the maximum operating current of each IP2003Apbf. obtain the soa temperature adjustments that match the operating conditions in the application from figs. 3, 4, 5 and 6. then, add the sum of the soa temperature adjustments to the tx axis intercept in fig 2. the example below explains how to calculate maximum power loss and soa. / # 890 3 # : ) 8: / # : ) 8 : .' 8,;<5 3 " 8 =< 8-> 8- ! # ') ? ! & ) 5 # ') ( # ) ,% 9! & ) 5 # ') ( # ) 9 ! & ) 5 # ') ( ( "1 ,9 ! & ) 5 # ') ( " ) )") * '+ ( " 8 ? ,% 9 ,9 , ? 120 10 20 30 40 50 60 70 80 90 100 110 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 0 102030405060708090100110120 pcb temperature (oc) output current (a) safe operating area v in = 12v v out = 1.3 v f sw = 1mhz l=0.3uh case temperature ( oc ) t x downloaded from: http:/// : t d(on) t d(off) pwm v sw 90% 10% 90% 10% ! & 0 " ? ! ./0# 0 @ ( # ) 7 - 9! ./0# 0 @ ( # ) - ! ./0# 0 @ ( ( "1 7 - ! ./0# 0 @ ( " ) - "# # @ 87 -a -7 - a - %- 0 8-b 8-c $( )) ' #)$ '$ ' $./0" @ ( " ( %- 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 0 1 02 03 04 05 06 07 08 09 01 0 01 1 01 2 0 pcb temperature (oc) output current (a) safe operating area v in = 12v v out = 1.3v f sw = 1mhz l=0.3uh t x 0 1 02 03 04 05 06 07 08 09 01 0 01 1 01 2 0 v sw p gnd prdy enable v dd a a dc v averag e input voltag e (v in ) average input current (i in ) average output current (i out ) averaging circuit v average output voltage (v out ) dc v average vdd voltage (v dd ) a average vdd current (i dd ) i p2003a p in = v in average x i in average p dd = v dd average x i dd average p ou t = v out average x i ou t average p loss = (p in + p dd ) - p out v in pw m downloaded from: http:/// @ one of the most critical elements of proper pcb layout with IP2003Apbf is the placement of the externalinput bypass capacitors and the routing of the connecting power tracks. # $% & it is recommended that the designer uses the following guidelines: 1. the diagram below suggests the addition of the input bypass capacitors either on the top side of the pcb (capacitors c1-c6) or top and bottom side (c7, c8), if placement on the bottom side is feasible. the amount of the input capacitors is based on the input ripple current handling requirement of the IP2003Apbf. to support 12a input rms current, based on 12v input, 1.3v and 40a output and 1mhz, the IP2003Apbf will require enough input ceramic capacitors to support the input rms ac current. these capacitors must be placed as close to the ipowir device as possible. 2. in the diagram below, observe the routing of the power tracks that connect the external bypass capacitors. 3. provide a mid-layer solid ground plane with connections to the top through vias. 4. refer to ir application note an-1029a to determine the size of the vias and the copper weight and thickness when designing the pcb. downloaded from: http:/// 8 ' (() 0.15 [.006] c 2. dime ns ions are s hown in millime t e rs [inche s ]. 3. cont rolling dime ns ion: millime t e r 1. dimens ioning & t olerancing per as me y14.5m-1994. not e s : b a 0.15 [.006] c 2x 2x top view package body. 5 primary datum c is seating plane. 6 bilat e ral t ole rance z one is applie d t o each s ide of t he 6 6 orientation cor ne r i d 11.00 [.433] 9.00 [.354] 2.31 [.0909] 2.13 [.0839] 4. land des ignat ion per jes d mo 222, s pp-010. (6) (8) y x (7) xy y (5) y x x (2),(3) xy 2.032 4.953 3.429 3.048 3.429 5.334 3.429 1.778 1.1430 1.1016 (1) 2.1016 1.1430 (4) 1.1430 1.2192 xy y x layout notes: 1. land pat t ern on us ers pcb s hould be an ident ical mirror image of t he pat t e rn s hown in t he bot t om view. 2. lands should be solder mask defined. c 5 side view (9),(10) xy 1.016 0.635 3.9116 8.509 1.9050 0.3556 0 bottom view 7.1773 3.253 0.332 8.6124 2.2243 1.2337 8.9248 6.9567 v dd 1.3593 enable 4.5183 0 p g n d v in v sw p g n d v sws2 v s w s 1 prdy pwm ' (*) 0508 IP2003A 2.5 [0.10] 2.0 [0.08] 6b7d downloaded from: http:/// + #$ % &'() * + ,-./0 . , & 0 ) / / 4 / ) &57' #$ 1 - 2 -- 32& ? , , ) / #$ !) ..** 4( *) 1 * 2 ( ) 2 5 1*61 % " &7' 31 01 6 " & 3 " 6 6 / 6 6 6 6 #$ "& . 7 86% 2 , - % () 8 )2 * 2 fig. 12: tape & reel information 1. out line conforms t o eia-481 & eia-541. IP2003A, lga not es : 12mm feed direction 24mm 0508 IP2003A 6b7d IP2003A 6b7d 0508 *0*2>+d0 downloaded from: http:/// ()'&)6 9/ :;),/)3 -22 a )6 ( ) 6 +->6 b) c * 2 . ->-4@ > ,c *2 . ->-4@+2 < 89: fig. 13: part marking the recommended reflow peak temperature not to exceed 260c. the total furnance time is approximately 5 minutes with approximately 10 seconds at the peak temperature. fig.14: recommended solder profile and stencil design 2. dime ns ions are s hown in millime t e rs . 3. this opening is based on using 150 micron stencil. 1. this view is stencil squeegee view not e s : if us ing different thickness s tencil, this opening f h y x g xy y e y x x b,c xy 1.9304 4.8514 3.3274 2.9464 3.3274 5.2324 3.3274 1.6764 0.9906 0.9492 a 1.9492 0.9906 d 0.9906 1.0668 xy y x i,j xy 0.9144 0.5334 a bc d e f g h i j needs to be adjusted accordingly stencil design downloaded from: http:/// |
Price & Availability of IP2003A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |